module uart(
    input     wire       sys_clk  ,
    input     wire       sys_rst_n,
    input     wire       rx       ,
    output    wire [5:0] sel      ,
    output    wire [7:0] seg      ,
    output    wire       tx  
);

wire    [7:0]   data   ;
wire            rx_vld ;

uart_rx u_rx(
.sys_clk    (sys_clk    ),
.sys_rst_n  (sys_rst_n  ),
.rx         (rx         ),
.rx_dout    (data       ),
.rx_vld     (rx_vld     ) 
);
uart_tx u_tx(
.sys_clk    (sys_clk    ),
.sys_rst_n  (sys_rst_n  ),
.tx_data    (data       ),
.rx_vld     (rx_vld     ),
.tx         (tx         )   
);

led_dynamic u_led_dynamic(
.sys_clk    (sys_clk    ),
.sys_rst_n  (sys_rst_n  ),
.data       (data       ),
.rx_vld     (rx_vld     ),

.sel        (sel        ),
.seg        (seg        )
);

endmodule